Lateral gan pn junction diode enabled by sidewall regrowth

ABSTRACT

Lateral PN junctions and diodes and transistors comprising lateral PN junctions and methods used in making such devices are disclosed. A method of fabricating a lateral PN junction, can comprise: conformally growing p−GaN material on a n−GaN vertical surface extending vertically from an n−GaN horizontal surface on an n−GaN drift layer to form a first PN junction, wherein the n−GaN horizontal surface extends horizontally from the n−GaN vertical surface and the n−GaN horizontal surface has a layer of dielectric material formed on the n−GaN horizontal surface that extends from the p−GaN surface.

CROSS REFERENCE TO RELATED APPLICATIONS

This non-provisional application claims priority to provisionalapplication No. 62/508,356 filed on May 18, 2017.

TECHNICAL FIELD

The present disclosure is directed in general to diodes, transistors andother semiconductor devices.

BACKGROUND OF THE DISCLOSURE

Junctions, such as PN junctions can be used in various devices such asdiodes and transistors. PN junctions have a p-doped region of asemiconductor adjacent to an n-doped region of a semiconductor. As adiode, PN junctions can stop the flow of current in one direction whileallowing flow in the opposite direction. In some transistors, two PNjunctions can be used to amplify a signal.

In various embodiments, as disclosed herein GaN PN diodes can befabricated with a vertical structure on GaN substrates, a lateralstructure on insulating substrates, or in other orientations, and the PNjunction in can be placed in the c-plane or in other planes.

SUMMARY OF THE DISCLOSURE

In a first aspect, a method of fabricating a lateral PN junction isprovided. The method comprising: conformally growing p−GaN material on an−GaN vertical surface extending vertically from an n−GaN horizontalsurface to form a first PN junction, wherein the n−GaN horizontalsurface extends horizontally from the n−GaN vertical surface and then−GaN horizontal surface has a layer of dielectric material formed onthe n−GaN horizontal surface that extends from the p−GaN surface.

In a second aspect, a method of fabricating a lateral PN junction isprovided. The method comprising: isotropically depositing a first layerof dielectric material on a n−GaN drift layer; patterning and etchingthe n−GaN drift layer to form a trench through the first layer ofdielectric material and into the n−GaN drift layer, wherein the trenchcomprises a bottom surface and a first sidewall; anisotropicallydepositing a second layer of dielectric material on the bottom surfaceof the trench and on the first layer of dielectric material;isotropically etching the trench resulting in n−GaN drift layer havingremaining first layer and second layer of dielectric material on anupper horizontal surface of the n−GaN drift layer and remaining secondlayer of dielectric material on the bottom surface of the trench and thefirst sidewall having exposed n−GaN material; conformally regrowingp−GaN material on the exposed n−GaN material of the first sidewall.

In a third aspect, a semiconductor comprising a lateral PN junction isprovided, the semiconductor comprising: an n−GaN horizontal surface; ann−GaN vertical surface extending vertically from the n−GaN horizontalsurface; a dielectric layer deposited on the n−GaN horizontal surfaceand contacting the n−GaN vertical surface; and a p−GaN layer extendinghorizontally from the n−GaN vertical surface to form a first PN junctiontherewith.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1a-g show processing steps of an embodiment disclosed herein.

FIG. 2 shows an scanning electron micrograph (SEM) of an embodiment of adevice at one processing step.

FIG. 3 shows an SEM of an embodiment of a device at one processing step.

FIG. 4a-c show SEMs of a embodiments of a device at a particularprocessing step.

FIG. 5 is a diagram of an embodiment disclosed herein.

FIG. 6 is a diagram of an embodiment of a vertical diode.

FIG. 7 is a diagram of a plan view of an embodiment of a vertical diode.

DETAILED DESCRIPTION

It should be understood at the outset that, although example embodimentsare illustrated below, the present technology may be implemented usingany number of techniques, whether currently known or not. The presenttechnology should in no way be limited to the example implementations,drawings, and techniques illustrated below. Additionally, the drawingsare not to scale, except when indicated otherwise by, for example,context.

As discussed herein, “vertical” means extending in a direction outwardfrom or perpendicular to a substrate non-edge surface and “horizontal”(whether contacting or not) means parallel to a substrate non-edgesurface. In some discussion, the designation of horizontal and verticalcan be made in terms of the orientation defined prior to removal of asubstrate, and in some cases, the material or surface being described as“horizontal” or “vertical” can be added after the removal of thesubstrate.

PN junctions and PN diodes can be fabricated from a variety ofsemiconductors doped with appropriate dopants. Preferably, PN junctionscan be fabricated from doped GaN or other suitable Group III-Group Vsemiconductors. Dopants for the Group III-Group V semiconductor caninclude silicon or oxygen or other suitable elements to produce ann-type semiconductor or magnesium or other suitable elements to producea p-type semiconductor.

In various embodiments, GaN PN junctions and diodes can be fabricatedwith a vertical structure, such as where a P-doped GaN material ispositioned above or below an N-doped GaN material, on GaN substrates, ora lateral structure, such as where a P-doped GaN material is positionedhorizontally in relation to an N-doped GaN material, on insulatingsubstrates. In some embodiments, the PN junction can be placed in thec-plane, however the PN junction can also in some embodiments be placedin another plane, such as the m-plane, the r-plane or the a-plane.

Preferable PN junctions and PN diodes can be fabricated as a lateraldevice, where the p-doped portion is located to one side of (e.g.,displaced horizontally or horizontally and vertically from) the n-dopedportion, rather than in a vertical arrangement of one on top of theother. Such lateral devices can be used for making GaN vertical devicestructures, such as GaN junction barrier Schottky (JBS) diodes and GaNSuperjunction (SJ) MOSFETs.

In some embodiments of fabricating a lateral PN junction or PN diode,planar (horizontal) surfaces can be masked while vertical surfaces, suchas trench sidewalls, stepped features or other surfaces having verticalrelief, can be exposed for regrowth of semiconductor material. Invarious embodiments, the semiconductor material can be a form of GaN orother Group III-Group V semiconductor or semiconductor alloy system suchas BN, BP, BAs, B₁₂As₂, AlN, AlP, AlAs, AlSb, GaP, GaAs, GaSb, In N,InP, InAs, InSb, Al_(x)Ga_(1-x)As, In_(x)Ga_(1-x)As, In_(x)Ga_(1-x)P,Al_(x)In_(1-x)As, Al_(x)In_(1-x)Sb, GaAsN, GaAsP, GaAsSb, AlGaN, AlGaP,InGaN, InAsSb, AlGaInP, AlGaAsP, InGaAsSb, InAsSbP, AlInAsP, AlGaAsN,InGaAsN, InAlAsN, GaAsSbN, BaInNAsSb, BaInAsSbP, etc. and combinationsthereof. The semiconductor material can be doped, such as to produce an“n” form or a “p” form, such as n−GaN or p−GaN. In some embodiments, theregrowth can regrow a “p” form such as p−GaN and the exposed surface canbe an “n” form, such as n−GaN, producing a PN junction. In someembodiments, the regrowth can regrow an “n” form such as n−GaN and theexposed surface can be a “p” form, such as p−GaN, producing a PNjunction. In some embodiments of regrowing semiconductor material toform a PN junction, vertical growth originating from the planar(horizontal) surface below and adjacent to the vertical surface (such asa trench bottom or a bottom of a step feature) can be prevented orlimited so as to reduce or eliminate dislocations generated bycompetitive growth on the vertical and horizontal planes.

In additional embodiments, methods can include Approach 1) laterallypatterned ion implantation and annealing processes to impart a laterallydoped region and Approach 2) laterally patterned selective areas foretch and epitaxy regrowth. These approaches can in some embodiments belimited by thermal stability of a GaN surface during the elevatedtemperature treatment for activation of dopants (Approach 1) and thepotential for leakage paths through dislocations and stacking faultsrelated to the competitive growth from the sidewall and the trenchbottom, local defects such as nitrogen vacancies introduced by selectiveetching processes prior to regrowth, introduction of impurities such ashigh density silicon, at the regrown PN junction interface, anddifficulty in achieving conformal epitaxy on the sidewall of etchedtrenches with given geometry (Approach 2).

Process Description

FIGS. 1a-h show an embodiment of a process flow of forming a lateral PNjunction. In FIG. 1a , a doped Group III-Group V semiconductor, such asan n−GaN drift layer 14 is located on a Group III-Group V substrate,such as a GaN substrate 12. Any suitable method for fabricating then−GaN drift layer can be used, such as metal organic chemical vapordeposition (MOCVD), molecular beam epitaxy (MBE) or hydride vapor phaseepitaxy (HVPE). In various embodiments, the dopant for the n−GaN layercan be any suitable atom, such as Si, Ge or O, and can have a level suchas 1×10¹⁰/cm³ to 1×10²⁰/cm³. Other semiconductor materials, such asGroup III-Group V semiconductors can be used to form the drift layer 14,but drift layer 14 will be referred to herein as n−GaN drift layer forconvenience, while a person of skill in the art would understand thatdifferent materials, such as other Group III-Group V semiconductors(such as those described herein) can be appropriately doped and used invarious embodiments as well and the n and p doping can be reversedbetween the layers as desired.

FIG. 1b shows a dielectric layer 26 deposited on an upper surface 48 ofthe n−GaN drift layer 14. Here, the dielectric layer can be deposited onthe entire upper surface 48 of the n−GaN drift layer 14 on the GaNsubstrate 12. Any suitable method for depositing the dielectric layer26, such as atomic layer deposition, metal-organic chemical vapordeposition, plasma-enhanced chemical vapor deposition, low-temperaturechemical vapor deposition, can be used. The dielectric material can beSiO₂, SiN or any other suitable dielectric that can provide the desiredcharacteristics of masking and/or electrical insulation.

FIG. 1c shows the wafer after it has been patterned and selective areasof the dielectric have been removed to form a patterned opening 10 inthe dielectric. Suitable methods of patterning and material removalinclude methods such as wet etch or plasma-based dry etch. In someembodiments, the material removal that occurs for FIG. 1c can alsoprogress into the n−GaN material 14 to at least some extent. After thepatterned opening 10 is formed, a trench 36 can be formed in n−GaN driftlayer 14, such as by using dielectric layer 26 on the upper horizontalsurface 48 of the n−GaN drift layer 14 as the etch mask. The deviceafter forming the trench 36 is shown in FIG. 1d . Suitable methods forforming the trench 36 can include methods of dry etching, such asCl-based plasma etch.

In some embodiments, it can be beneficial to use a dry etch process withprocessing conditions selected, such as by varying the power inputand/or by varying the vapor composition and pressure, such as the vaporpressure of chlorine species, to reduce or eliminate the occurrence of(1) grass formation (such as due to micro-masking); (2) micro-trenchingat the corners of the trenches; and/or (3) surface roughness on theetched sidewall. An example of a dry-etched trench is shown in FIG. 2.The trench in FIG. 2 was made by dry etching of GaN using dielectric asthe etch mask.

After trench formation, in one embodiment, some or all of the horizontalsurfaces (such as the surfaces that are the c-plane of the n−GaN 14) canbe masked while some or all of the vertical surfaces (such as thesurfaces that are the m-plane of the n−GaN 14) are exposed. In oneembodiment, another layer of dielectric can be deposited over the wafer,preferably using an anisotropic physical-vapor-deposition process, suchas e-beam evaporation. (FIG. 1e .) In a preferred embodiment, theanisotropic deposition can result in less deposition on the trenchsidewalls as compared with the planar surface, providing a thicker layerof dielectric on horizontal surfaces than on vertical surfaces. Afterthe second dielectric deposition, an isotropic etch (such as wet etch,high pressure plasma etch or a buffered oxide etch (such as an HF dip))can be performed to remove dielectric from the trench sidewalls 34, 40,with dielectric remaining on the horizontal surfaces such as one or moreof the trench bottom 38 and the upper horizontal surface 48, as in FIG.1f . In some embodiments, a dielectric layer 22 can remain covering thebottom of the trench 38 and the upper horizontal surface 48 of the n−GaNdrift layer, and the dielectric material can be removed completely fromthe trench sidewalls 34, 40 (except where the edge of the dielectriclayer 22 covering the bottom of the trench 38 contacts the sidewalls 34,40.)

Next p−GaN 16 can be regrown on the trench sidewall(s) 34, 40, formingPN junctions 42, 44 with the exposed n−GaN of the sidewalls 34, 40, asshown in FIG. 1g . Suitable methods for regrowth of p−GaN can includemetal-organic chemical vapor deposition. In preferable embodiments,regrowth of the p−GaN material will result in regrown p−GaN materialwith low or zero incidence of voids. FIG. 3 is a scanning electronmicrograph of a cross-section of GaN regrown in a 1.5 μm-deep trench(the outline of the original trench is indicated by dashed lines) wherethe bottom of the trench was not covered with dielectric during theregrowth step. The regrown GaN filled the trench and overgrew on top ofthe SiO₂ mask and was covered by another layer of dielectric grown bymetal-organic chemical vapor deposition (MOCVD.) Also visible are twovoids that formed in the trench during the regrowth. Without wishing tobe limited by theory, it is believed that the voids occurred as a resultof the competition between the vertical GaN growth from the trenchbottom and the lateral GaN growth from the upper portion of the trenchsidewalls.

Again, without wishing to be limited by theory, it is believed aconformal growth on the sidewall would be beneficial in avoidingformation of voids, although some degree of non-conformity can betolerated for at least some applications. It is also believed thatincreases in trench depth and/or increases in aspect ratio can increasethe difficulty in achieving conformal growth and conformal growth withlow or non-occurrence of voids/defects. In some particular embodiments,such as where trench depth approaches or exceeds about 0.1 to about 10μm, and/or where the width is or exceeds about 0.1 to about 10 μm,conformal growth can be particularly difficult to achieve, due to bothgroup III and group V atoms requiring kinetic energy high enough (highertemperature) to move freely on the sidewall. Conditions favoringconformal growth for trench depths up to about 1, 2, 3, 4, 5, 6, 7 or 8μm or more and/or where the width is or exceeds about 0.1 to about 10 μmcan include lower pressures, higher temperatures and higher V/III ratio,and the presence of a dielectric layer on or covering portions of or theentirety of the trench bottom can allow greater flexibility in selectingprocess conditions and can simplify achieving conformal sidewall growthand conformal sidewall growth with reduced incidence of defects.

FIG. 4a-c shows SEMs of GaN regrown on the sidewalls of 4 μm deeptrenches (FIGS. 4a and c ) and 4 μm tall fins (FIG. 4b ). To prepare thespecimens of FIGS. 4a-c , n+GaN substrates were patterned with SiO₂masks. After dry etching (e.g. plasma etch, such as reactive ion etch orinductively coupled plasma techniques), only GaN sidewalls and thetrench bottom were exposed to regrowth. In this experiment, the planarregion at the bottom of the vertical structure (such as the trenchbottom) was not covered by a dielectric mask. In some embodiments, theregrowth can favor or be limited to the sidewalls in preference to theplanar bottom region (e.g. trench bottom) by selection of the aspectratio of the trench and the regrowth conditions. For deep trenches, suchas where the aspect ratio (depth/width) is greater than or equal toabout 2, the regrowth conditions can be controlled to such that theregrowth occurs primarily or exclusively on the sidewalls rather thanthe bottom. Without wishing to be limited by theory, it is believed thatthe vapor species that diffuse into the trench are consumed before inregrowth on the sidewalls before they can reach the bottom. In some suchembodiments, the sidewall regrowth can be conformal, near conformal ornon-conformal, such as where the regrowth at the top of the trench isgreater than that further down in the trench. While in someapplications, this non-conformality can be undesirable, in someapplications the degree of non-conformality can be acceptable. In thisexperiment, the trench bottom (or lateral region adjacent a verticalfeature) was rough due to non-ideal etching. Conformal undoped GaNregrowth on sidewalls with all lateral orientations was achieved for allthree samples. The growth conditions consist of low pressure, hightemperature and high VIII ratio. FIG. 4a shows the top view of a trenchafter sidewall regrowth. FIG. 4b shows regrowth on sidewalls of finpatterns. The regrown layer in FIG. 4c shows the regrowth can beperformed on non-polar planes with any orientation. Regrowth onnon-polar planes with any orientation allows the fabrication ofunconstrained placement on an m-plane or a p-plane of lateral PNjunction diodes on a device.

Conformal sidewall regrowth techniques disclosed herein can beimplemented either with or without a barrier of dielectric material onthe adjacent horizontal surface (such as a trench bottom with regrowthon a trench sidewall, or where the sidewall regrowth is on a steppedarea of a device or chip.) For embodiments where a barrier of dielectricmaterial is present, the presence of the barrier of dielectric materialcan further enhance lateral regrowth such as by reducing or eliminatingthe possibility of voids and other structural defects being formedduring regrowth and by electrically isolating the bottom of the regrownmaterial from the horizontal surface. A barrier of dielectric can beachieved by covering the trench bottom (or the horizontal surfaceadjacent to a step in the surface of the device) with an SiO₂ mask andperforming lateral regrowth along the SiO₂ mask, as shown in FIG. 5. Asshown in FIG. 5, no GaN growth on c-plane 64 occurs (direction of GaNgrowth/regrowth is in the direction of the arrows). All the regrown GaN66 originates from the non-polar plane 68 on the sidewall 34. Theseconformal sidewall regrowth techniques can in various embodiments beutilized in the fabrication of a vertical diode and a verticaltransistor, including those with a lateral PN junction.

Vertical Diode

Power PN diodes can be fabricated utilizing techniques disclosed hereinfor the fabrication of lateral PN junctions. FIG. 6 shows across-sectional of a schematic of one embodiment of a lateral PNjunction. FIG. 7 shows a plan view of the lateral diode of FIG. 6. InFIG. 6, a PN junction 54 is located under and in contact with an n+GaNsubstrate 12. On the n+GaN substrate 12 is an n−GaN drift layer 14, witha series of trenches 36 fabricated into the n−GaN drift layer 14. Withineach of the trenches 36 are a dielectric layer 22 at the bottom of thetrench 38 and p−GaN material 16 on the sidewalls 34 of the trenchresulting in a PN junction at the sidewall. On the top of the n−GaNdrift layer 14 is dielectric layer 26. The lateral PN junctions 42 shownin FIG. 6 can be used for two purposes in this device structure. One isfor forming a main junction in the center trench 36 (with p-ohmiccontacts 30) to provide forward conduction and reverse blocking; theother is for forming guard rings at the edge of the device to provideedge termination (trenches 36 without p-ohmic contacts 30). Thegeometric parameters, e.g. junction depth of the PN diode and guard ringspacing, number of guard rings, trench dimensions, etc., can be adjustedto vary the device performance.

n−GaN Material

Various grades of n−GaN material can be used in devices disclosedherein. However, in some embodiments, it can be preferable to utilizehigher quality GaN drift layer material, such as those having a defectdensity of less than about 1×10¹⁶/cm³ and/or a dislocation density ofless than about 1×10⁸/cm². Suitable GaN drift layer material can invarious embodiment be grown by any suitable method such as bymetalorganic chemical vapor deposition, however other methods can alsobe used in various embodiments. In some embodiments, higher or lowerquality GaN drift layer material can be used, such as where the defectdensity is less than about 1×10²⁰/cm³, or about 1×10¹⁸/cm³, or about1×10¹⁷/cm³, or about 1×10¹⁵/cm³, or about 1×10¹⁴/cm³ and or thedislocation density of less than about 1×10¹⁰/cm², 1×10⁹/cm², 1×10⁷/cm²,1×10⁶/cm², 1×10⁵/cm² where the defect density and the dislocationdensity are chosen separately. In some embodiments, the quality of theGaN drift layer can be selected based upon the voltage class of thedevice desired, such as with higher quality GaN drift layer material(lower defect density and/or lower dislocation density) for highervoltage devices.

PN Diodes

PN diodes can benefit from utilization of lateral PN junctions, such asthose disclosed herein, as well as the quality of the GaN drift layer(e.g., GaN drift layer having very low density of structure defects andimpurities); edge termination suitable for preventing prematurebreakdown at the edge of the device; and lateral regrowth in narrow anddeep trenches to meet the junction depth and pitch size requirementshaving high quality lateral regrowth where the defect density and/orimpurity level are low at the regrowth interface. In some embodiments,the MOCVD growth conditions can be chosen for achieving high crystalquality, such as having defect density and/or dislocation density asdescribed herein and low impurity density GaN drift layer, yielding600˜1200V class Schottky diodes and MOSFETs. Edge termination for GaNvertical devices in some embodiments can utilize techniques such astrench etch or implantation damage. Preferred embodiments of edgetermination can utilize a guard ring structure embedded into the GaNmaterial or the n−GaN drift layer. In some implementations, a guard ringstructure can be achieved with no additional process steps or very fewadditional process steps, and can be scaled to high voltages. Asdisclosed herein, doped GaN sidewall growth can be achieved deep and/ornarrow trenches.

In various embodiments, a vertical wall or a trench or a series oftrenches can be formed in GaN or other Group III-Group V material forthe preparation of PN junctions and diodes as described herein, such aswhere the vertical wall or the sides of the trenches follow planes ofthe crystal structure of the material. In some embodiments, a trench canbe open-ended at one or both ends. In some embodiments, the trench canbe closed at one or both ends. In some embodiments, one or both closedends can be concave or convex in reference to the trench. In someembodiments, a series of vertical walls can form series of trenches,where at least some of the ends of the walls are not connected to otherwalls (such as in FIG. 4b ). In some embodiments, then ends of wall canfollow the hexagonal shape of a wurtzite crystal form and/or can beconvex or concave in relation to the wall. In some embodiments, bothends of a trench can be closed such that the sides and ends form ahexagonal structure, such as by following the planes of the crystal,such as a hexagonal wurtzite structure. In some embodiments, one end ofa trench can be open and the other end can be closed, where the closedend follows two planes of a hexagonal wurtzite structure and the sidesof the trench follow two other planes of a hexagonal wurtzite structure.In various embodiments, various benefits can be achieved throughselection of the shape of the trench and by selection of the crystalplanes used for the device, such as one or more of high packing density,low specific on-resistance, exposure of only one crystal plane (limitingthe exposure of either the m-plane or the a-plane during sidewallregrowth is possible and can simplify the selection of growthconditions.) In some embodiments of a closed trench, the side walls andthe closed ends can form a regular hexagon having sides of equivalent ornear equivalent lengths. In some embodiments, a vertical wall or a wallin a trench can be used which follows one crystal plane only or where avertical wall or a wall in a trench one crystal plane followed byfollowing one or more different crystal planes intersecting the first,such as to form one or more turns or bends in the vertical wall or awall in the trench. In some such embodiments involving a trench, thesecond wall of the trench can follow a parallel path of the first wallfor a portion of the trench length or for the entirety of the trenchlength.

In various embodiments of the devices and methods described herein, itcan be beneficial to polish surfaces prior to regrowth. Polishing canresult in better purity and in better quality devices, such as thosethat can handle higher voltage. Preferred methods of polishing caninclude polishing utilizing a chloride precursor (e.g. HCl, Cl₂, BCl₃,etc.) In some further preferred embodiments, polishing can be followedby commencing regrowth without exposing the polished surface to theoutside atmosphere or completely eliminating the vacuum. In some suchpreferred embodiments, during the entire period of polish throughregrowth, the material is kept under vacuum in a controlled atmosphereand the time lag between polishing and beginning regrowth is less than30 minutes, or less than 20 minutes or less than 10 minutes or less than5 minutes. In some embodiments, it can be beneficial to include crackedammonia or another nitrogen source during the polishing step or aportion of the polishing step and/or during at least a portion of theregrowth step, such as to remove or suppress the formation of nitrogenvacancies (“VN”) and/or assist in growing a layer of VN-free undopedGaN. In some embodiments, the polishing step can remove several of thetop monolayers of GaN (or other Group III-Group V material), such as thetop tens of monolayers (e.g. 10-20, 20-30, 30-40, 40-50 or moremonolayers.) In some embodiments, the polishing step can reduce siliconimpurity concentration below 10¹⁴ cm⁻² or below 10¹³ cm⁻² or below 10¹²cm⁻² or lower at the regrown interface.

Modifications, additions, or omissions may be made to the systems,apparatuses, and methods described herein without departing from thescope of the inventive concepts. The components of the systems andapparatuses may be integrated or separated. Moreover, the operations ofthe systems and apparatuses may be performed by more, fewer, or othercomponents. The methods may include more, fewer, or other steps.Additionally, steps may be performed in any suitable order. As used inthis document, “each” refers to each member of a set or each member of asubset of a set.

What is claimed is:
 1. A method of fabricating a lateral PN junction,the method comprising: conformally growing p−GaN material on a n−GaNvertical surface extending vertically from an n−GaN horizontal surfaceon an n−GaN drift layer to form a first PN junction, wherein the n−GaNhorizontal surface extends horizontally from the n−GaN vertical surfaceand the n−GaN horizontal surface has a layer of dielectric materialformed on the n−GaN horizontal surface that extends from the p−GaNsurface.
 2. The method of claim 1, wherein the n−GaN vertical surface isa non-polar plane of GaN.
 3. The method of claim 1, wherein the n−GaNhorizontal surface contacts the layer of dielectric material, and then−GaN horizontal surface comprises a c-plane of GaN.
 4. The method ofclaim 1, wherein the layer of dielectric material is formed byanisotropic deposition of dielectric material on the n−GaN horizontalsurface resulting in a thicker layer of dielectric present on the n−GaNhorizontal surface than a layer of dielectric present on the n−GaNvertical surface, followed by isotropic removal of a portion of thedielectric material resulting in the layer of dielectric formed on then−GaN horizontal surface remaining.
 5. The method of claim 1, whereinthe n−GaN vertical surface is substantially free of dielectric materialafter the isotropic removal of dielectric material.
 6. The method ofclaim 4, wherein an upper dielectric layer extends horizontally from anupper edge of the n−GaN vertical surface away from a direction of growthof the p−GaN material.
 7. The method of claim 6, wherein an n+GaNsubstrate is located below the n−GaN drift layer and an n-ohmic contactis located below the n+GaN substrate, and further comprising forming ap-ohmic contact on an upper surface of the p−GaN material.
 8. The methodof claim 1, wherein the n−GaN vertical surface is a first sidewall of atrench formed in an n−GaN drift layer and the n−GaN horizontal surfaceforms the bottom of the trench.
 9. The method of claim 8, wherein thetrench further comprises a second sidewall opposing the first sidewallwith the layer of dielectric material extending from the first sidewallto the second sidewall, and the method further comprising conformallygrowing p−GaN material on the second sidewall to form a second PNjunction, the second PN junction extending toward the first PN junction.10. A method of fabricating a lateral PN junction, the methodcomprising: isotropically depositing a first layer of dielectricmaterial on a n−GaN drift layer; patterning and etching the n−GaN driftlayer to form a trench through the first layer of dielectric materialand into the n−GaN drift layer, wherein the trench comprises a bottomsurface and a first sidewall; anisotropically depositing a second layerof dielectric material on the bottom surface of the trench and on thefirst layer of dielectric material; isotropically etching the trenchresulting in n−GaN drift layer having remaining first layer and secondlayer of dielectric material on an upper horizontal surface of the n−GaNdrift layer and remaining second layer of dielectric material on thebottom surface of the trench and the first sidewall having exposed n−GaNmaterial; conformally regrowing p−GaN material on the exposed n−GaNmaterial of the first sidewall.
 11. A semiconductor comprising a lateralPN junction, the semiconductor comprising: an n−GaN horizontal surface;an n−GaN vertical surface extending vertically from the n−GaN horizontalsurface; a dielectric layer deposited on the n−GaN horizontal surfaceand contacting the n−GaN vertical surface; and a p−GaN layer extendinghorizontally from the n−GaN vertical surface to form a first PN junctiontherewith.
 12. The semiconductor of claim 11, wherein the n−GaN verticalsurface is a non-polar plane of GaN.
 13. The semiconductor of claim 11,wherein the n−GaN horizontal surface comprises a c-plane of GaN.
 14. Thesemiconductor of claim 11, further comprising: a second n−GaN verticalsurface extending vertically from the n−GaN horizontal surface andfacing the n−GaN vertical surface; a second p−GaN layer extendinghorizontally from the second n−GaN vertical surface toward the n−GaNvertical surface, the second p−GaN layer and the second n−GaN verticalsurface forming a second PN junction.